Intel and Micron Technologies have begun sampling 8GB NAND chips based on next-generation 20-nanometer process technology, which reduces the size of flash memory devices by 30 to 40 percent in comparison with the companies' existing 25nm chips. Measuring just 118mm square, the tiny multilevel-cell NAND chips are destined for deployment in smartphones, tablets and solid-state drives.
IM Flash Technologies (IMFT) -- the NAND flash joint venture established by Intel and Micron in early 2006 -- is slated to begin mass production of the new 8GB chips in the second half of 2011. The partners also expect to begin sampling a 16GB device later this year that will enable manufacturers to construct solid-state storage devices with 128GB of memory that are smaller than a U.S. postage stamp.
"Our innovation and growth opportunities continue with the 20nm NAND process, enabling Micron to deliver cost-effective, value-added solid-state storage solutions for our customers," said Micron Vice President Glenn Hawk.
As consumers snap up web tablets in increasing numbers this year and beyond, research firm iSuppli expects the use of NAND flash memory in these popular devices to dramatically increase. The proportion of NAND flash use among tablets -- when measured against the total supply of NAND memory overall -- will jump from 4.3 percent in 2010 to 11.8 percent this year and reach 16 percent by 2014, the firm's analysts predicted.
According to DRAMeXchange, NAND flash makers Toshiba and SanDisk reported damage to their plants following last month's horrific earthquake and tsunami in Japan, which caused the average selling price of NAND chips to rise five percent to 15 percent at the end of March. Moreover, electricity brownouts and raw-material shortages are expected to continue disrupting NAND production in Japan during the current quarter.
However, IMFT's mass production of next-generation 20nm NAND chips is slated to take place outside the stricken region. "The 20nm NAND is currently being manufactured at the IMFT Fab in Lehi, Utah," noted Micron spokesperson Kirstin Bordner. And later on, the joint venture's 20nm NAND production will begin "at the IMFT Fab in Manassas, Va., and at IMFT in Singapore," Bordner added.
Increasing Fab Production
The 40 percent reduction in chip size afforded by the new 20nm technology will enable tablet and smartphone manufacturers to improve performance through the addition of a bigger battery, a larger screen, or additional chips. Moreover, Intel and Micron expect to derive benefits by shrinking NAND lithography to the latest technology node.
Among other things, the companies said the move to 20nm is a cost-effective method for increasing Fab output. In comparison with current 25nm technology, the next-generation process will deliver about 50 percent more gigabyte capacity from the factories, observed Micron Director of Strategic NAND Marketing Kevin Kilbuck.
"This shrink is well ahead of our competitors -- some have just announced production on a process equivalent to our 25nm -- and keeps us solidly in the leadership position for NAND development," Kilbuck wrote in a blog.
Semiconductor process reductions require tinier, more complex cells, which potentially could lead to lower chip performance and endurance. However, the new 20nm chips from Intel and Micron feature new technology that will will enable these devices to meet the same endurance and performance specifications governing current-generation 25nm NAND devices, Kilbuck observed.
"We're also continuing our pattern of keeping error correction code (ECC) requirements a generation lower than the competition," Kilbuck wrote. "Our 20nm NAND will have similar ECC requirements to some competitors' current NAND products, meaning they won't require more ECC from the controller."